High-k dielectrics (k>10) are known to increase gate capacitance without generally causing unacceptably high gate leakage currents for metal oxide semiconductor (MOS) devices. However, a high-k dielectric layer may not be compatible with gate electrodes formed using traditional polysilicon gates, but can be compatible with certain metal gates. Moreover, metal gates are increasingly used for smaller geometry devices because polysilicon depletion effects in traditional polysilicon gate devices can significantly degrade device characteristics and overall integrated circuit performance.
One process that provides an alternative to polysilicon gates for complementary metal oxide semiconductor (CMOS) devices, is a replacement gate process that can be used to form gate electrodes comprising one or more metal layers. In that process, at least one polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is then filled with at least one metal layer. In another process, a fully silicided gate process (FUSI) can be used to form gate electrodes from metals. In the FUSI process, at least a portion of the polysilicon layer on a gate oxide, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is then filled with at least one silicide capable metal. Thermal processing can then be used to fully silicide the remaining polysilicon material.
However, issues arise when working with p-type and n-type doped polysilicon layers. In particular, the varying dry and/or wet etch rates of p-doped and n-doped polysilicon relative to each other make the process of etching the trenches needed for the formation of a metal gate or silicide gate electrode difficult and inconsistent. The result is that generally either the p-type or the n-type gate will be exposed to a significant amount of overetch, resulting in damage to the spacer features or any other exposed features on the wafers. This resulting damage can degrade performance or even render a device unusable.
Accordingly, there is a need for an improved method for forming replacement gate electrodes for CMOS integrated circuits.